The ever decreasing dimensions of semiconductor devices such as field effect transistors continue to present new challenges for gate design and manufacture. As gate lengths reduce, the thickness of the gate insulating layers that are used must also decrease. Conventionally, SiO2 has been used as a gate insulator. However, since SiO2 layers thinner than around 1.0-1.5 nm suffer from unacceptably strong gate leakage effects, attention in recent times has turned to alternative structures that include high-K dielectric materials.
High-K dielectric materials allow thicker insulating layer dimensions to be employed, while retaining relatively high values of gate capacitance.
As illustrated in FIG. 1, known high-K gate structures use a bi-layered arrangement comprising a dielectric layer 4 of high-K gate material and an interfacial layer 2, which is located in between high-K dielectric layer 4 and the channel region 6 of the field effect transistor 10. As shown in FIG. 1, the transistor 10 also includes conventional source and drain regions 12, located on either side of the channel region 6, in the substrate 14.
The purpose of the interfacial layer 2 shown in FIG. 1, which typically comprises a layer of relatively low-K SiO2, is to act as a seed for the growth of the high-K dielectric layer 4 (which can be crystalline or amorphous) during manufacture. The gate electrode 8 itself is formed on top of the high-K dielectric layer 4. The gate electrode 8 may typically comprise a metal or polysilicon layer. Spacers 5 are typically provided on either side of the gate.
Present high-K gate technologies are unable to meet the demands of the International Technology Roadmap for Semiconductors (ITRS), which foresees an 8 Å CETinv (Capacitance Equivalent Thickness under inversion) for high performance applications in 2011 (this is equivalent to a standard oxide (SiO2) thickness of 4-5 Å). In present high-K gate structures of the kind shown in FIG. 1, the interfacial layer 2 is typically formed with a thickness of 7-12 Å. Moreover, the high-K dielectric layer 4 thickness is limited by the fact that known high-K materials cannot at present be grown homogenously below a thickness of around 12-15 Å.
It is an object of this invention to address at least some of the limitations noted above in respect of existing gate structures incorporating high-K dielectrics.